Setting Up Microblaze on the Nexys4 FPGA Board

This is an introduction to setting up a microblaze processor for the Nexys4 Artix-7, using Vivado 2014.1 .

1. Create a new project. (Image 1)

2. Press Next

3. Press Next, name the project Hello_World, and select create project subdirectory (Image 2)

4. Press Next, select RTL Project (Image 3)

5. Press Next

6.Press Next

7. Press Next

8. At the Default Part screen, select the parts, corresponding to the image (Image 4).Press Next.

9. Press Finish

10. In The Flow Navigator, under IP Integrator, click "Create Block Design" (Image 5)

11. Change Design name to be system (Image 6)

12. Click on "Add IP" in the green bar at the top (Image 7)

13. Begin to type "Microblaze" and select the processor (Image 8).

A block representing the processor is added to the block design.

14. Click on "Run Block Automation" and choose the /microblaze_0 dropdown (Image 9)

15. Change the "Local Memory" to 32Kb and the "Debug Module" to "Debug & UART" (Image 10) and click OK. It generates several additional blocks and places them on the board.

16. Double click on the block labeled "clocking wizard" (Image 11)

17. Change the clock source to "single ended clock capable pin" (Image 12)

18. Click on "Run Block automation" and choose /clk_wiz_1/clk_in1 Press ok

19. Click on "Run Block Automatic" and choose /reset_rtl_0 and select "Active Low" Press OK

20. Click on "Run Block Automation" and choose /clk_wiz_1/reset and select "Active high" Press OK

**Note** Your design might have generated with different names i.e. reset_rtl_0 might be reset_rtl

21. Expand the "Constraints" folder, under the "sources" tab. Right click and select "Add Sources" (Image 13)

22. Select "Add or Create Constraints" and press next.

23. Press "Add Files" and navigate to where the file "Nexys4_Master.xdc" is saved. If you need this file, download it from http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1184&Prod=NEXYS4

24. Press OK and finish, make sure the box to copy the file to your local project is selected.

25. Open the constraints file, and uncomment lines: 8,9,10, 59,60, 194 and 195

26. Modify the port names in those properties, to match the port names in your Block Diagram

set_property PACKAGE_PIN E3 [get_ports clock_rtl] 
set_property IOSTANDARD LVCMOS33 [get_ports clock_rtl] 
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clock_rtl] 

set_property PACKAGE_PIN P4 [get_ports reset_rtl_0 ] 
set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl_0 ] 

set_property PACKAGE_PIN E16 [get_ports reset_rtl]  
set_property IOSTANDARD LVCMOS33 [get_ports reset_rtl] 

27. Make sure to save the updated .xdc file (Press Ctrl-S)

28. Right click on "system.bd" in the sources window. Select "Create HDL Wrapper"

29. Expand the system_wrapper and Right click on "system.bd" in the sources window. Select "Generate output products"

30. Click "Generate Bitstream" and wait for the synthesis and implementation to complete.

31. Click on "Open implemented design" and press ok. (Image 14)

32. Once the design opens. Select File > Export > Export Hardware for SDK

33. Check the box "Launch SDK", and "Export Hardware" and "Include Bitstream"

34. Once the SDK is open. Select File > New > Application Project

35. Name your project hello, press ok (Image 15)

36. Select the test project "Hello World" (Image 16) and press ok

37. Turn on the FPGA and select: Xilinx tools > Program FPGA

38. Leave the settings alone and press "Program"

39. Select your project folder called "hello". Open the src folder and open helloworld.c

40. Select Run > Debug Configurations. Under STDIO Tab, check connect STDIO to Console, and choose JTAG UART from the dropdown list. (Image 17)

41. Flip Switch 15 on the Nexys4 board (This turns off reset, if you press Run, and there is an error, try flipping the switch the other direction). (Image 18)

42. Right click on "hello" folder, select: Run As > Launch on Hardware (GDB) The console should say "Hello World"