Speed Regulating PWM Fan Motor Controller

The GreenPAK™ SLG46531 device can be used in high power applications by controlling a FET to drive a motor i.e. a PWM DC-DC buck converter. In this Instructable, we will show how to design a programmable closed-loop speed-regulating PWM fan controller using RPM feedback and I2C. The average percent error is less than 2.5%, and the min and max were less than 15%. These can be improved by increasing resolution at the cost of increased settling time.

Below we described the steps needed to understand how to program this device. However, if you just want to get the result of programming, download GreenPAK Designer software (a part of the Go Configure™ Software Hub) to view the already completed GreenPAK design file. Plug the GreenPAK Development Kit to your computer and hit the program to create the system.

The three wires of a 3-wire fan are VDD, GND, and a tachometer OUT.

The motor which turns the fan is brushless and uses about 0.2A at 5.0V. In this circuit, the motor speed of the fan is proportional to the input power, which is pulse modulated by a PFET to the power supply. The PFET gate is controlled by the GreenPAK PWM output, PIN18, as shown in Figure 1. The PWM output is determined by the Hall Effect RPM feedback.

A Hall Effect Sensor is positioned between two coils in the fan and is the tachometer feedback out of the fan into the GreenPAK. Each edge of the Hall Effect Sensor signifies one rotation. By measuring the time between two rotations, we can calculate the speed at which the motor is rotating and adjust the power to the motor accordingly.

As shown in Figure 1, the supply is at 5V, which is within GreenPAK’s operating limit. The circuit below is a DC-DC buck converter using one FET on the high side, a clamping diode, and an LC filter.

This design uses all eight states of the ASM. The states are labeled as in Figure 2. The initial state is the Reset state. In the Reset state, the PWM output is forced low.

Due to inertia, a fan does not start moving until we overcome static friction. That minimum duty cycle is typically 30%.

When the ASM is enabled, we transition to an ‘Overdrive’ state, where the output is allowed to be driven at maximum power, 100% duty cycle, for 3 seconds. This initial kick is meant to overcome the static friction, allowing the motor to start spinning.

From there, we arbitrarily choose to enter the PWM Up state. If the RPM is too high, the GreenPAK will self-correct and move to PWM Down. The state machine continues to toggle between PWM Down and PWM Up. As we reach a steady-state, the toggling will become more and more stable.

In the event that the RPM desired is too low or too high, the GreenPAK will eventually reach either 100% or 0% duty cycle. To prevent the PWM from wrapping around, the output is gated at a ‘Stop High’ or ‘Stop Low’ state. In these states, the PWM is forced high and low.

‘Buffer Low’ and ‘Buffer High’ are intermediary states to prevent unwanted ASM state transitions. The state machine uses edge detectors for ‘Stop Low’ and ‘Stop High’. If the PWM should reverse directions at this point, the very first period will incur an edge. If there was no Buffers state, we would look from one Stop state to another Stop state immediately. Therefore, the Buffer state is an intermediary state to prevent looping.

The main inputs to the ASM are ‘Decrease PWM’ and ‘Increase PWM’, two inverted signals. They signify when to increase or decrease the PWM width as shown in Figure 4. ‘Increase PWM’ transitions the ASM from PWM Down to PWM Up and ‘Decrease PWM’ transitions the ASM from PWM Up to PWM Down.

FSM0 is the RPM frequency counter. In frequency detect mode, the time between two input edges is measured and compared to the counter data. If the length is longer, the speed is too slow. If the length is shorter, the speed is too fast. The output of FSM0 regulates the DC-DC buck to pump more or less power to the fan circuit.

FSM0 is configured as both edge frequency detectors because the tachometer used in this application, US1881, is a latching hall effect sensor. Meaning each rotation toggles the tachometer output. Therefore each edge, whether falling or rising, represents one 360 degrees rotation. For this example, the target RPM has a period of 40 ms.

The input to the edge detectors is an AND of the Set and Reset signals. By checking for an overlap, we are able to know when the duty cycle has reached 100% or 0%. The edge detect outputs then transition the ASM to ‘Stop High’ and ‘Stop Low’.

Since the very first PWM output Set and Reset signals overlap by default, we include intermediary states to prevent the states from transitioning incorrectly.

The PWM duty cycle is controlled by a Set and Reset signal which come from the output of the CNT5/DLY5 and CNT6/DLY6. The settings are identical as seen in Figure 6.

In order to increase and decrease the PWM, we shift the Set and Reset signals relative to each other to achieve a shorter or longer duty cycle. Refer to Figure 8 timing diagram. Depending on the current state, one of two CNT/DLY blocks will gain an extra clock, shifting the output to the left, earlier in time. If Set shifts, the PWM increases. If Reset shifts, the PWM decreases. This is controlled by the signals ‘Reset’ and ‘Set’ as seen in Figure 7.

The extra clock occurs every 50 periods, allowing time for the mechanical world to catch up with the electrical signals. This is the update period, set by CNT4/DLY4. Every update period, the pipe delay and 2-bit LUT2 generate a pulse into the 3-bit LUT0 and 3-bit LUT1 IN0 inputs. If XORed with the normal clock source, we will generate an extra pulse.

Only four ASM outputs are used. ‘Shift_CNT6’ and ‘Shift_CNT5’ go into the SR Counter logic and control the shifting. They are used to select which CNT gets an extra clock, representing the current direction that the PWM is going in.

As seen in the ASM Output Table of Figure 9, Reset and Set are both High if we are counting up and both Low when counting down. To stop extra clock counting, Reset and Set are opposites. Reset is high and Set is Low. This makes sure that they both choose the regular clock source.

‘Force 0’ and ‘Force 100’ indicate when the PWM logic has reached 100% and 0% and masks out the SR Latch. ‘Force 0 forces the PFET closed for Stop Low, Buffer Low, and Reset states. ‘Force 100 forces the PFET open for Stop High, Buffer High and Overdrive states.

3-bit LUT2 is the SR Latch. If CNT6_out is logic 1, the latch is set. If CNT5_out is logic 1, the Latch is reset. 3-bit LUT6 gates the SR Latch. If Set High is high, the output is forced high. If Set low is high, the output is forced low. Both signals will never be high at the same time. If both signals are low, use the inverse of the 3-bit LUT2.

To change the desired RPM, use I2C to write the counter value of FSM0. The word address is located at address 0xC5 and 0xC6.

Refer to the example in Table 1 below. If we want to write to FSM0 the counter value 0xDD, the command would be:

[0xSA 0xC5 0xE0 0x2E] for example 1

[0xSA 0xC5 0x40 0x1F] for example 2

Where SA is the slave address.

To convert from RPM to counter data, use the equation below:

counter data = OSC / RPM

The counter data depends on the GreenPAK internal OSC. In this design, the OSC should ideally be 2 MHz / 8 = 250 kHz. To get an RPM frequency of 25 Hz, the period must be 40 ms, which corresponds to a counter data of 9998.

Because the Actual OSC was measured to be 253 kHz, we end up with 25.3 Hz instead of 25 Hz.

The percent error was 2.4%, 1.0%, and 0.5% from the above three examples. The longer the device is running, the better the average percent error. Some error is due to OSC trim, which in our case was measured to be 253kHz instead of 250kHz. The PWM will take some time to ramp up or down until it reaches a steady-state. After reaching steady-state, the state machine will flip flop between the ‘PWM Up’ and ‘PWM Down’ which causes the PWM output to jitter around the average.

This causes the min and max frequency to jump around the average depending on the PWM resolution. In the above examples, the percent error of the mins and max frequencies were at worst, 15%. To decrease this error, we can increase the CNT5 and CNT6 counter value such that each increment would be a smaller PWM width, allowing for better frequency control but slower settling time.

The function below was taken after many seconds, when the PWM output has reached a steady state.

In steady-state, the state machine is switching from PWM Up to PWM Down rhythmically.

We can see that the RPM input has a frequency of 11.4 Hz or 88ms. However, since the Hall effect sensor is a latching device, every edge is being interpreted as a revolution. FSM0 is configured to detect both edges. Therefore, the actual RPM frequency is twice at 22.8 Hz or 45ms. This is right around our 40ms target, which was set by the counter value in FSM0.

Channel 1 (yellow) – PIN#18 (PWM Out)

Channel 2 (light blue) – PIN#3 (RPM)

Channel 3 (magenta) – Fan Input Voltage

Figure 13 shows the functionality when the FSM0 counter data is set to 12000. We can see the Hall effect frequency is 9.42 Hz, which implies an RPM of 18.84 Hz.

Figure 14 shows the functionality when the FSM0 counter data is set to 8000. We can see the Hall effect frequency is 14.8 Hz, which implies an RPM of 29.6 Hz.

The breadboard prototype of the PWM Fan is illustrated above. The breadboard on the left has the inductor, PFET, diode, and capacitors. The GreenPAK IC is placed on the development tool evaluation board.

The breadboard on the right connects the GreenPAK external connectors to the Hall Effect Sensor, which has to be powered continuously.

In the first image below, the fan is stopped because the PWM circuit is Disabled. In the second image, the Fan is running because the PWM circuit is Enabled.

Conclusion
This speed-regulating PWM fan motor controller project is an example of how the ASM can be used in a feedback loop to control an external motor. We use the frequency detector function to easily create a watchdog on the Hall effect input. Then, we use I2C to change the reference frequency. The entire digital control logic is implemented in the PAK device such that, due to the use of the ASM, it can be easily tweaked.