Video Interfacing With FPGA Using VGA

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Some of you might have already gone through my other blog: Design of VGA Controller in VHDL. This time I am writing a blog on designing a complete video system and also we will design a VGA Controller in System Verilog this time. We will design a system that will drive your monitor with a color pattern video using VGA from your FPGA.

Note: I have updated and release the new version of IP: VGA Controller v1.2 in my new blog. It has run-time configuration support and enhanced features. Feel free to use the newer IP, which was tested with more sophisticated test platform: HD monitor with text pattern generator.

If you don't want run-time configuration support and need lighter VGA Controller IP, proceed with the below blog.

Our Video System predominantly has three modules:

• VGA Controller
• Data Generator
• Pixel-clock enable generator

VGA Controller provides the necessary timing signals to drive the monitor through VGA port. VGA Controllers internally generates timing signals based on some thing called pixel frequency. Most monitors run at 60 Hz refresh rate, so you have to calculate pixel frequency according to that. For 640x480, it would be around 25 MHz. Couple of useful resources:

• Pixel clock frequency calculator
• VGA timing standards

VGA Controller also controls flow of video data through VGA port. Video data is generated from the data generator. Pixel frequency clock can be derived from the system clock on your board; either using MMCM/PLL or by generating a strobe or a clock enable from the system clock using counters. KINDLY AVOID USING INTERNAL CLOCK DIVIDERS AS THIS DIDN'T WORK WHILE I WAS DOING FPGA PROTOTYPING.

I implemented this on Basys-3 board which has a minimalistic DAC based on resistors. If you have a dedicated DAC on your development board like ADV71xx, you may need a couple of extra signals from your VGA Controller like 'blank' and 'sync on green'.

This module generates RGB data that forms the color patterns. The module's data output is controlled by VGA Controller. RGB-444 format color data was used by me as Basys-3 doesn't support RGB-888. The module generates all 12-bit color combinations as frames.

This is the module to generate a one cycle long pulse @ 25 MHz from 100 MHz system clock used on the board. This pulse is sampled by VGA Controller for generating sync signals. I used this logic instead of MMCM/PLL for ease of portability and to be make the video system stand-alone RTL.

The Video System and VGA Controller are both timing verified for 100 MHz and FPGA proven cores (On Basys-3 and Vivado 2018). Generate the bitstream and map the pins to the VGA ports on your board. Connect the monitor using VGA cable and press reset to get a nice color pattern displayed on the monitor tada ! :-)

If the video doesn't comes up, just troubleshoot:

• VGA timings are correct or not.
• VGA sync polarities are correct or not (may vary in some monitors).
• Monitor supports auto resolution detect and runs at 60 Hz or not.
• Properly generated bitstream without any timing and DRC violations.
• VGA cable working or not.

Please find all the attached files including the xdc for Basys-3 implementation.

• VGA Controller Module.
• Video System Top Module.
• IP Documentation.
• XDC for Basys-3 users.

For any queries: iammituraj@gmail.com

Regards,

Mitu Raj

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