ToplevelHDL Project Status
Project File: ClockMult.xise Parser Errors: No Errors
Module Name: ToplevelHDL Implementation State: Synthesized
Target Device: xc9572-7PC44
  • Errors:
X 1 Error (1 new)
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Feb 6 17:48:40 2014X 1 Error (1 new)00
Translation ReportOut of DateThu Feb 6 15:00:00 2014000
CPLD Fitter Report (Text)Out of DateThu Feb 6 15:00:02 201401 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentThu Feb 6 18:28:02 2014
Post-Fit Simulation Model Report  

Date Generated: 02/07/2014 - 14:50:36