Toplevel Project Status (02/06/2014 - 12:09:33)
Project File: ClockMult.xise Parser Errors: No Errors
Module Name: Toplevel Implementation State: Fitted
Target Device: xc9572-7PC44
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentThu Feb 6 14:14:01 2014000
Translation ReportCurrentThu Feb 6 14:14:06 2014000
CPLD Fitter Report (Text)CurrentThu Feb 6 14:14:07 201401 Warning (1 new)0
Power Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateThu Feb 6 14:23:53 2014
Post-Fit Simulation Model Report  

Date Generated: 02/06/2014 - 14:26:23