ToplevelHDL Project Status | |||
Project File: | ClockMult.xise | Parser Errors: | No Errors |
Module Name: | ToplevelHDL | Implementation State: | Synthesized |
Target Device: | xc9572-7PC44 |
|
X 1 Error (1 new) |
Product Version: | ISE 14.7 |
|
No Warnings |
Design Goal: | Balanced |
|
|
Design Strategy: | Xilinx Default (unlocked) |
|
|
Environment: | System Settings |
|
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Feb 6 17:48:40 2014 | X 1 Error (1 new) | 0 | 0 | |
Translation Report | Out of Date | Thu Feb 6 15:00:00 2014 | 0 | 0 | 0 | |
CPLD Fitter Report (Text) | Out of Date | Thu Feb 6 15:00:02 2014 | 0 | 1 Warning (1 new) | 0 | |
Power Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Current | Thu Feb 6 18:28:02 2014 | |
Post-Fit Simulation Model Report |