cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: Toplevel Date: 2- 6-2014, 2:14PM Device Used: XC9572-7-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 6 /72 ( 8%) 6 /360 ( 2%) 4 /144 ( 3%) 0 /72 ( 0%) 7 /34 ( 21%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 2/18 1/36 1 2/90 2/ 9 FB2 2/18 1/36 1 2/90 2/ 9 FB3 1/18 1/36 1 1/90 1/ 8 FB4 1/18 1/36 1 1/90 1/ 8 ----- ----- ----- ----- 6/72 4/144 6/360 6/34 * - Resource is exhausted ** Global Control Resources ** Global clock net(s) unused. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 1 1 | I/O : 7 28 Output : 6 6 | GCK/IO : 0 3 Bidirectional : 0 0 | GTS/IO : 0 2 GCK : 0 0 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 7 7 ** Power Data ** There are 6 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'Toplevel.ise'. ************************* Summary of Mapped Logic ************************ ** 6 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State CLK_4P 1 1 FB1_2 1 I/O O STD FAST CLKx3 1 1 FB1_8 4 I/O O STD FAST CLK_0 1 1 FB2_2 35 I/O O STD FAST CLK_3N 1 1 FB2_8 38 I/O O STD FAST CLK_1N 1 1 FB3_2 11 I/O O STD FAST CLK_2P 1 1 FB4_2 24 I/O O STD FAST ** 1 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use CLK_IN FB2_15 43 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 1/35 Number of signals used by logic mapping into function block: 1 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) CLK_4P 1 0 0 4 FB1_2 1 I/O O (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 2 I/O (unused) 0 0 0 5 FB1_6 3 I/O (unused) 0 0 0 5 FB1_7 (b) CLKx3 1 0 0 4 FB1_8 4 I/O O (unused) 0 0 0 5 FB1_9 5 GCK/I/O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 6 GCK/I/O (unused) 0 0 0 5 FB1_12 (b) (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 7 GCK/I/O (unused) 0 0 0 5 FB1_15 8 I/O (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 9 I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: CLK_IN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CLK_4P X....................................... 1 1 CLKx3 X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 1/35 Number of signals used by logic mapping into function block: 1 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 (b) CLK_0 1 0 0 4 FB2_2 35 I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 36 I/O (unused) 0 0 0 5 FB2_6 37 I/O (unused) 0 0 0 5 FB2_7 (b) CLK_3N 1 0 0 4 FB2_8 38 I/O O (unused) 0 0 0 5 FB2_9 39 GSR/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 40 GTS/I/O (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 42 GTS/I/O (unused) 0 0 0 5 FB2_15 43 I/O I (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 44 I/O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: CLK_IN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CLK_0 X....................................... 1 1 CLK_3N X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 1/35 Number of signals used by logic mapping into function block: 1 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) CLK_1N 1 0 0 4 FB3_2 11 I/O O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 12 I/O (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 13 I/O (unused) 0 0 0 5 FB3_9 14 I/O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 18 I/O (unused) 0 0 0 5 FB3_12 (b) (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 19 I/O (unused) 0 0 0 5 FB3_15 20 I/O (unused) 0 0 0 5 FB3_16 (b) (unused) 0 0 0 5 FB3_17 22 I/O (unused) 0 0 0 5 FB3_18 (b) Signals Used by Logic in Function Block 1: CLK_IN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CLK_1N X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 1/35 Number of signals used by logic mapping into function block: 1 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) CLK_2P 1 0 0 4 FB4_2 24 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 25 I/O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 26 I/O (unused) 0 0 0 5 FB4_9 27 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 28 I/O (unused) 0 0 0 5 FB4_12 (b) (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 29 I/O (unused) 0 0 0 5 FB4_15 33 I/O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 34 I/O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: CLK_IN Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CLK_2P X....................................... 1 1 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** CLK_0 <= CLK_IN; CLK_1N <= NOT CLK_IN; CLK_2P <= CLK_IN; CLK_3N <= NOT CLK_IN; CLK_4P <= CLK_IN; CLKx3 <= CLK_IN; Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9572-7-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9572-7-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 CLK_4P 23 GND 2 TIE 24 CLK_2P 3 TIE 25 TIE 4 CLKx3 26 TIE 5 TIE 27 TIE 6 TIE 28 TIE 7 TIE 29 TIE 8 TIE 30 TDO 9 TIE 31 GND 10 GND 32 VCC 11 CLK_1N 33 TIE 12 TIE 34 TIE 13 TIE 35 CLK_0 14 TIE 36 TIE 15 TDI 37 TIE 16 TMS 38 CLK_3N 17 TCK 39 TIE 18 TIE 40 TIE 19 TIE 41 VCC 20 TIE 42 TIE 21 VCC 43 CLK_IN 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572-7-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25