--Highest level component that connects all lower sub moduels together
--@author Sam Malicoat, Ryan Kendall

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity FINAL1 is
                Port ( CLK : in STD_LOGIC;
                       TimeSig : in STD_LOGIC;
                       Switch: in STD_LOGIC_VECTOR(6 downto 0);
                       Display : out STD_LOGIC_VECTOR (6 downto 0);
                       LED : out STD_LOGIC_VECTOR (15 downto 0);
                       Enable : out STD_LOGIC_VECTOR (3 downto 0));
end FINAL1;

architecture Behavioral of FINAL1 is

component Seg7 
                port (input : in STD_LOGIC_VECTOR (11 downto 0);
                      CLK : in STD_LOGIC;
                      Display : out STD_LOGIC_VECTOR (6 downto 0);
                      Enable : out STD_LOGIC_VECTOR (3 downto 0));
end component;

component ConvertHex2Dec 
                Port ( Hex : in STD_LOGIC_VECTOR (6 downto 0);
                       Dec : out STD_LOGIC_VECTOR (11 downto 0));
end component;

component  LedFlip 
                Port ( TimeSig : in STD_LOGIC;
                       BPM : in STD_LOGIC_VECTOR(6 downto 0);
                       Tick : in STD_LOGIC;
                       LED : out STD_LOGIC_VECTOR (15 downto 0));
end component;

signal BPM:STD_LOGIC_VECTOR(11 downto 0);
signal DecToSeg:STD_LOGIC_VECTOR(11 downto 0);
signal BetweenHexAndSeg:STD_LOGIC_VECTOR(11 downto 0);

begin

Convert: ConvertHex2Dec port map(Hex=>switch(6 downto 0),
                                 Dec=>BetweenHexAndSeg);

DecToSeg<=BetweenHexAndSeg;

DisplaySeg : Seg7 port map (input => DecToSeg,
                            CLK => CLK,
                            Enable => Enable,
                            Display => Display);
         
LedChange : LedFlip port map(
                            TimeSig=>TimeSig,
                            BPM=>Switch(6 downto 0),
                            Tick=>CLK,
                            LED=>LED);      
     
end Behavioral;