----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:18:34 12/01/2014 
-- Design Name: 
-- Module Name:    FinalSimon - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
---------------------------------------------------------------------------------
-- GLOBAL DIAGRAM
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity global is
Port (CLK : in std_logic;
    	RESET : in std_logic;
		INPUT : in std_logic;
		BTN : in std_logic_vector (3 downto 0);
		OUTPUT : out std_logic_vector (3 downto 0);
		GLO_OUTPUT : out std_logic_vector (3 downto 0);
		SEGMENTS : out std_logic_vector (7 downto 0);
		DISP_EN : out std_logic_vector (3 downto 0));

end global;

architecture SIMON of global is

	component display_FSM is
	port (CLK : in std_logic;
			REDO : in std_logic;
			RESET : in std_logic;
			D_INPUT : in std_logic;
			HARD_RESET : out std_logic;
			D_OUTPUT : out std_logic_vector (3 downto 0);
			CMP_OUTPUT : out std_logic_vector (3 downto 0);
			COUNTER_MAX : out std_logic);
  
	end component;
	
	component check_input_FSM is
	port (C_COUNTER_MAX : in std_logic;
			CLK : in std_logic;
			RESET : in std_logic;
			INPUT : in std_logic_vector (3 downto 0);
			CMP_LED : in std_logic_vector (3 downto 0);
			BTN_ENABLE : in std_logic;
			CHK_LED : out std_logic_vector (3 downto 0);
			REDO : out std_logic;
			GAME_OVER : out std_logic);
  
	end component;

	component game_over_FSM is
	port (GO : in std_logic;
			clk : in std_logic;
			HARD_RESET : in std_logic;
			GO_SEGMENTS : out std_logic_vector (7 downto 0);
			GO_DISP_EN : out std_logic_vector (3 downto 0);
			BTN_ENABLE : out std_logic);
  
	end component;
	
signal tmp_COUNTER_MAX : std_logic;	
signal tmp_OUTPUT : std_logic_vector (3 downto 0);
signal tmp_GO : std_logic;
signal tmp_REDO : std_logic;
signal tmp_HARD_RESET : std_logic;
signal tmp_BTN_ENABLE : std_logic;

begin

	display0 : display_FSM port map (CLK => CLK, REDO => tmp_REDO, RESET => RESET, D_INPUT => INPUT, HARD_RESET => tmp_HARD_RESET,
												D_OUTPUT => OUTPUT, CMP_OUTPUT => tmp_OUTPUT, COUNTER_MAX => tmp_COUNTER_MAX);
												
	check0 : check_input_FSM port map (C_COUNTER_MAX => tmp_COUNTER_MAX, CLK => CLK, RESET => RESET, INPUT => BTN, BTN_ENABLE => tmp_BTN_ENABLE, 
													CMP_LED => tmp_OUTPUT, CHK_LED => GLO_OUTPUT, REDO => tmp_REDO, GAME_OVER => tmp_GO);
													
	game_over0 : game_over_FSM port map (GO => tmp_GO, CLK => CLK, HARD_RESET => tmp_HARD_RESET, GO_SEGMENTS => SEGMENTS, GO_DISP_EN => DISP_EN, BTN_ENABLE => tmp_BTN_ENABLE);

end SIMON;
	
----------------------------------------------------------------------------------
-- DISPLAY LED FSM
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity display_FSM is
port (CLK : in std_logic;
		REDO : in std_logic;
      RESET : in std_logic;
		D_INPUT : in std_logic;
		HARD_RESET : out std_logic;
		D_OUTPUT : out std_logic_vector (3 downto 0);
		CMP_OUTPUT : out std_logic_vector (3 downto 0);
		COUNTER_MAX : out std_logic);
  
end display_FSM;


architecture behavioral of display_FSM is

	component BlinkANDCounter is
	Port( START : in std_logic;
			REDO : in std_logic;
			RESET : in std_logic;
			CLK : in std_logic;
			LED : out std_logic_vector (3 downto 0);
			CMP_LED : out std_logic_vector (3 downto 0);
			MAX_COUNT : out std_logic_vector (7 downto 0));
						
	end component;


type state_type is (wait1, display1);  --type of state machine.
signal current_state, next_state : state_type;  --current and next state declaration.

signal count : std_logic_vector (7 downto 0);

begin

	blink_disp0 : BlinkANDCounter port map (START => D_INPUT, REDO => REDO, RESET => RESET, CLK => CLK, LED => D_OUTPUT,
															CMP_LED => CMP_OUTPUT, MAX_COUNT => count);
	

process (clk, D_INPUT, reset)

begin
 
if (reset = '1' or D_INPUT = '0') then
  current_state <= wait1;  --default state on reset.
  
elsif (rising_edge(clk)) then
  current_state <= next_state;   --state change.

end if;

end process;

--state machine process.
process (current_state, D_INPUT, count)
begin

HARD_RESET <= '0';
COUNTER_MAX <= '0';

  case current_state is
 
    when wait1 =>        --when current state is "s0"
	 
	 if(D_INPUT = '1') then
		
		next_state <= display1;
		
	 elsif (D_INPUT = '0') then
	 
	 HARD_RESET <= '1';
	 
      next_state <= wait1;
	
	 else null;
	 
    end if;   

    when display1 =>       --when current state is "s1"
	 
	 if(count = "11111111") then
	 
	 COUNTER_MAX <= '1';
	 
		next_state <= wait1;
    
	 else

      next_state <= display1;
		
    end if;
	 
  end case;
end process;

end behavioral;

----------------------------------------------------------------------------------------------
-- CHECK INPUT FSM / USER INPUT FSM
----------------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity check_input_FSM is
port (C_COUNTER_MAX : in std_logic;
		CLK : in std_logic;
      RESET : in std_logic;
      INPUT : in std_logic_vector (3 downto 0);
		CMP_LED : in std_logic_vector (3 downto 0);
		BTN_ENABLE : in std_logic;
		CHK_LED : out std_logic_vector (3 downto 0);
      REDO : out std_logic;
		GAME_OVER : out std_logic);
  
end check_input_FSM;

architecture behavioral of check_input_FSM is

	component user_commence is
	Port (USER_ENABLE : in std_logic;
			CLK : in std_logic;
			BTN : in std_logic_vector (3 downto 0);
			BTN_ENABLE : in std_logic;
			LED : out std_logic_vector (3 downto 0);
			Q : out std_logic);

	end component;

	component Comparator is
   Port ( COMPARE_ENABLE : in std_logic;
			 CLK : in STD_LOGIC;
			 X : in  STD_LOGIC_VECTOR (3 downto 0);
          Y : in  STD_LOGIC_VECTOR (3 downto 0);
          EQ : out  STD_LOGIC);
			  
	end component;
	

type state_type is (wait2, check2);  --type of state machine.
signal current_state, next_state : state_type;  --current and next state declaration.

signal tmp_EQ : std_logic;
signal tmp_Q : std_logic;

begin

process (clk, RESET)

begin
 
if (RESET = '1') then
  current_state <= wait2;  --default state on reset.
  
elsif (rising_edge(clk)) then
  current_state <= next_state;   --state change.

end if;

end process;

	user0 : user_commence port map (USER_ENABLE => C_COUNTER_MAX, CLK => CLK, BTN => INPUT, BTN_ENABLE => BTN_ENABLE, LED => CHK_LED, Q => tmp_Q);
	compare0 : comparator port map (COMPARE_ENABLE => tmp_Q, CLK => CLK, X => INPUT, Y => CMP_LED, EQ => tmp_EQ);


--state machine process.
process (current_state, INPUT, C_COUNTER_MAX, tmp_EQ)

begin

REDO <= '0';
GAME_OVER <= '0';
	
  case current_state is
 
    when wait2 =>        --when current state is "s0"
	 
	 if(C_COUNTER_MAX = '1' and INPUT /= "0000") then
	 
      next_state <= check2;
    
	 else
      
		next_state <= wait2;
		
    end if;   

    when check2 =>        --when current state is "s1"
		
		if(tmp_EQ = '1') then
		
		REDO <= '1';	
			
			next_state <= wait2;

		else
		
		GAME_OVER <= '1';

			next_state <= check2;
			
		end if;
  end case;
end process;

end behavioral;


----------------------------------------------------------------------------------------------
-- GAME OVER FSM
----------------------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity game_over_FSM is
port (GO : in std_logic;
		clk : in std_logic;
		HARD_RESET : in std_logic;
		GO_SEGMENTS : out std_logic_vector (7 downto 0);
		GO_DISP_EN : out std_logic_vector (3 downto 0);
		BTN_ENABLE : out std_logic);
  
end game_over_FSM;

architecture behavioral of game_over_FSM is

	component end_game is
	Port (END_ENABLE : in std_logic;
			HARD_RESET : in std_logic;
			CLK : in std_logic;
			SEGMENTS : out std_logic_vector (7 downto 0);
			DISP_EN : out std_logic_vector (3 downto 0));
	
	end component;

type state_type is (gameover3, wait3);  --type of state machine.
signal current_state, next_state : state_type;  --current and next state declaration.

begin

process (clk)

begin
 
  
if (rising_edge(clk)) then
  current_state <= next_state;   --state change.

end if;

end process;

	end0 : end_game port map (END_ENABLE => GO, HARD_RESET => HARD_RESET, CLK => CLK, SEGMENTS => GO_SEGMENTS, DISP_EN => GO_DISP_EN);

--state machine process.
process (current_state, GO)

begin

BTN_ENABLE <= '1';

  case current_state is
  
    when wait3 =>        --when current state is "s0"
     
	 if(GO = '1') then

      next_state <= gameover3; 
		
    
	 else
		
		 next_state <= wait3;

	 end if;   

    when gameover3 =>        --when current state is "s1"
    
	 if(GO = '0') then
	 
      next_state <= wait3;
    
	 else
	 
	 BTN_ENABLE <= '0';
	 
      next_state <= gameover3;
		
    end if;
	 
  end case;
end process;

end behavioral;


----------------------------------------------------------------------------------
-- Blink LED until Counter Overflows
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity BlinkANDCounter is
	Port( START : in std_logic;
			REDO : in std_logic;
			RESET : in std_logic;
			CLK : in std_logic;
			LED : out std_logic_vector (3 downto 0);
			CMP_LED : out std_logic_vector (3 downto 0);
			MAX_COUNT : out std_logic_vector (7 downto 0));
						
end BlinkANDCounter;

architecture Behavioral of BlinkANDCounter is

	component random is
	port (clk : in std_logic;
			random_num : out std_logic_vector (3 downto 0));
	
	end component;

	component counter_clk_div is
	port (clk : in std_logic;
			sclk : out std_logic);
			
	end component;


	signal tmp : std_logic_vector(3 downto 0);
	signal slow_count : std_logic;
	signal count : std_logic_vector (7 downto 0);

begin

	random0 : random port map(CLK => CLK, random_num => tmp);
	
	count_clock : counter_clk_div port map(CLK => CLK, SCLK => slow_count);
	
	process (tmp, START, RESET, slow_count, count, REDO)
	
begin

	if (reset = '1' or REDO = '1') then
		count <= "00000000"; LED <= "0000"; -- can hold LEDs
	
	elsif (START = '1' and count /= "11111111") then
	
		if (rising_edge(slow_count)) then
		
		count <= count + 1;

				if (count = x"01" and ((tmp = "0001") or (tmp = "0101") or (tmp = "1001") or (tmp = "1101"))) then 
				LED <= "0001"; CMP_LED <= "0001";
		
				elsif (count = x"01" and ((tmp = "0010") or (tmp = "0110") or (tmp = "1010") or (tmp = "1110"))) then 
				LED <= "0010"; CMP_LED <= "0010";
	
				elsif (count = x"01" and ((tmp = "0011") or (tmp = "0111") or (tmp = "1011") or (tmp = "1111"))) then 
				LED <= "0100"; CMP_LED <= "0100";
	
				elsif (count = x"01" and ((tmp = "0100") or (tmp = "1000") or (tmp = "1100"))) then 
				LED <= "1000"; CMP_LED <= "1000";

				end if;	
				
		end if;
		
	elsif (count = "11111111") then
		count <= count; LED <= "0000";

	end if;

end process;

MAX_COUNT <= count;

end Behavioral;


---------------------------------------------------------------------------------
-- User Button Input
---------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity user_commence is
	Port (USER_ENABLE : in std_logic;
			CLK : in std_logic;
			BTN : in std_logic_vector (3 downto 0);
			BTN_ENABLE : in std_logic;
			LED : out std_logic_vector (3 downto 0);
			Q : out std_logic);

end user_commence;

architecture my_start of user_commence is

begin

process (BTN, CLK, USER_ENABLE, BTN_ENABLE)

begin

if (BTN_ENABLE = '1') then

	if (USER_ENABLE = '0') then
	LED <= "0000"; 

	elsif (USER_ENABLE = '1') then

			if (rising_edge(CLK)) then

				if (BTN = "1000") then
				LED <= "1000"; Q <= '1';

				elsif (BTN = "0100") then
				LED <= "0100"; Q <= '1';
	
				elsif (BTN = "0010") then
				LED <= "0010"; Q <= '1';
	
				elsif (BTN = "0001") then
				LED <= "0001"; Q <= '1';
	
				else
				LED <= "0000"; Q <= '0';
	
			end if;
		end if;
		

	end if;

else	
	LED <= "0000"; Q <= '0';

end if;

end process;

end my_start;


----------------------------------------------------------------------------------
-- Comparator
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Comparator is
    Port ( COMPARE_ENABLE : in std_logic;
			  CLK : in STD_LOGIC;
			  X : in  STD_LOGIC_VECTOR (3 downto 0);
           Y : in  STD_LOGIC_VECTOR (3 downto 0);
           EQ : out  STD_LOGIC);
			  
end Comparator;

architecture Behavioral of Comparator is

begin

process (COMPARE_ENABLE, CLK, X, Y)

begin

if (COMPARE_ENABLE = '1') then

	if(rising_edge(CLK)) then
	
		if (X = Y) then
			EQ <= '1'; 
	
		elsif (X /= Y) then
			EQ <= '0'; 
		
		end if;
	
	end if;
	
end if;

end process;

end Behavioral;


----------------------------------------------------------------------------------
-- Game Over State
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity end_game is
	Port (END_ENABLE : in std_logic;
			HARD_RESET : in std_logic;
			CLK : in std_logic;
			SEGMENTS : out std_logic_vector (7 downto 0);
			DISP_EN : out std_logic_vector (3 downto 0));
	
end end_game;

architecture my_game_over of end_game is

begin

process (CLK, HARD_RESET, END_ENABLE)

begin

if (rising_edge(CLK)) then
	if (END_ENABLE = '1' and HARD_RESET = '0') then
	
		DISP_EN <= "1110"; SEGMENTS <= "01100001";

	else
		DISP_EN <= "1111"; SEGMENTS <= "11111111";
	
	end if;

end if;

end process;

end my_game_over;


----------------------------------------------------------------------------------
-- Random Number Generator
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity random is

generic ( width : integer :=  4 );

	port (clk : in std_logic;
			random_num : out std_logic_vector (width-1 downto 0));
		
end random;

architecture Behavioral of random is

	component random_clk_div is
		Port (CLK : in std_logic;
				SCLK : out std_logic);
	
	end component;

signal slow_random : std_logic;

begin

	random_with_clk : random_clk_div port map (CLK => CLK, SCLK => slow_random);

process(slow_random)

variable rand_temp : std_logic_vector(width-1 downto 0):=(width-1 => '1',others => '0');
variable temp : std_logic := '0';

begin

if(rising_edge(slow_random)) then

temp := rand_temp(width-1) xor rand_temp(width-2);
rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0);
rand_temp(0) := temp;

end if;

random_num <= rand_temp;

end process;

end Behavioral;


-----------------------------------------------------------------------
-- Module to divide the clock 
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity random_clk_div is
    Port (  clk : in std_logic;
           sclk : out std_logic);
			  
end random_clk_div;


architecture my_clk_div of random_clk_div is

   constant max_count : integer := (21000000);  
   signal tmp_clk : std_logic := '0'; 
	
begin
   my_div: process (clk,tmp_clk)              
      variable div_cnt : integer := 0;   
   begin
      if (rising_edge(clk)) then   
         if (div_cnt = MAX_COUNT) then 
            tmp_clk <= not tmp_clk; 
            div_cnt := 0; 
         else
            div_cnt := div_cnt + 1; 
         end if; 
      end if; 
      sclk <= tmp_clk; 
   end process my_div; 
end my_clk_div;

-----------------------------------------------------------------------
-- Module to divide the clock 
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity counter_clk_div is
    Port (  clk : in std_logic;
           sclk : out std_logic);
			  
end counter_clk_div;


architecture my_clk_div of counter_clk_div is

   constant max_count : integer := (62500);
   signal tmp_clk : std_logic := '0'; 
	
begin
   my_div: process (clk,tmp_clk)              
      variable div_cnt : integer := 0;   
   begin
      if (rising_edge(clk)) then   
         if (div_cnt = MAX_COUNT) then 
            tmp_clk <= not tmp_clk; 
            div_cnt := 0; 
         else
            div_cnt := div_cnt + 1; 
         end if; 
      end if; 
      sclk <= tmp_clk; 
   end process my_div; 
end my_clk_div;