Toplevel_mijnvisionproject Project Status (09/15/2015 - 22:25:24)
Project File: vision.xise Parser Errors: No Errors
Module Name: Toplevel_mijnvisionproject Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
32 Warnings (32 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 431 11,440 3%  
    Number used as Flip Flops 431      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 737 5,720 12%  
    Number used as logic 728 5,720 12%  
        Number using O6 output only 364      
        Number using O5 output only 88      
        Number using O5 and O6 276      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 9      
        Number with same-slice register load 6      
        Number with same-slice carry load 3      
        Number with other load 0      
Number of occupied Slices 260 1,430 18%  
Number of MUXCYs used 292 2,860 10%  
Number of LUT Flip Flop pairs used 759      
    Number with an unused Flip Flop 401 759 52%  
    Number with an unused LUT 22 759 2%  
    Number of fully used LUT-FF pairs 336 759 44%  
    Number of unique control sets 29      
    Number of slice register sites lost
        to control set restrictions
57 11,440 1%  
Number of bonded IOBs 43 102 42%  
    Number of LOCed IOBs 43 43 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 2      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.27      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentvr 18. sep 10:35:08 2015031 Warnings (31 new)9 Infos (9 new)
Translation ReportCurrentvr 18. sep 10:35:25 2015000
Map ReportCurrentvr 18. sep 10:36:28 201501 Warning (1 new)6 Infos (6 new)
Place and Route ReportCurrentvr 18. sep 10:36:56 2015003 Infos (3 new)
Power Report     
Post-PAR Static Timing ReportCurrentvr 18. sep 10:37:09 2015004 Infos (4 new)
Bitgen ReportCurrentvr 18. sep 10:37:34 2015000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentvr 18. sep 10:37:36 2015
WebTalk Log FileCurrentvr 18. sep 10:37:47 2015

Date Generated: 09/18/2015 - 10:39:05