--Addes to 4 bit numbers together using smaller sub moduels to do the actualy addition
--@author Sam Malicoat, Ryan Kendall
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity Full_Adder is
    Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
           B : in STD_LOGIC_VECTOR (3 downto 0);
           Result : out STD_LOGIC_VECTOR (3 downto 0));
end Full_Adder;

architecture Behavioral of Full_Adder is

   component SubFullAdder port (A, B, Cin : in STD_LOGIC;
                                SUM,Cout : out STD_LOGIC);

   end component;
  
   signal sCin0,sCout0,sCout1,sCout2,sCout3: STD_LOGIC;    
 
begin

    sCin0 <= '0';


    A0: SubFullAdder port map( 
       A => A(0),
       B => B(0),
       Cin => sCin0,
       Sum => Result(0),
       Cout => sCout0);
  
    A1: SubFullAdder port map( 
       A => A(1),
       B => B(1),
       Cin => sCout0,
       Sum => Result(1),
       Cout => sCout1);
   
    A2: SubFullAdder port map( 
       A => A(2),
       B => B(2),
       Cin => sCout1,
       Sum => Result(2),
       Cout => sCout2);

    A3: SubFullAdder port map( 
        A => A(3),
        B => B(3),
        Cin => sCout2,
        Sum => Result(3),
        Cout => sCout3);                                               
       
       
 
end Behavioral;