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-- Engineer: Benjamin Yee amd Hasham Ali
-- 
-- Create Date: 11/29/2015 07:15:11 PM
-- Design Name: 
-- Module Name: Source - Behavioral
-- Project Name: Tally Counter
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Source is
    Port ( PressureA : in STD_LOGIC;
           PressureB : in STD_LOGIC;
           SEG : out STD_LOGIC_VECTOR (7 downto 0);
           AN : out STD_LOGIC_VECTOR (3 downto 0);
           Clear : in STD_LOGIC;
           Led : out STD_LOGIC_vector(1 downto 0);
           Binary_state : out STD_LOGIC_vector(1 downto 0);
           clk : in STD_LOGIC);
    end Source;

architecture Behavioral of Source is
    
    component sseg_dec is 
            Port (     ALU_VAL : in std_logic_vector(7 downto 0); 
                       SIGN : in std_logic;
                       VALID : in std_logic;
                       CLK : in std_logic;
                       DISP_EN : out std_logic_vector(3 downto 0);
                       SEGMENTS : out std_logic_vector(7 downto 0));
    end component sseg_dec;
    
    component clk_div2 is
            Port (  clk : in std_logic;
                   sclk : out std_logic);
    end component clk_div2;
    
    component FSM is   
        Port ( PressureA : in STD_LOGIC;
               PressureB : in STD_LOGIC;
               clk : in STD_LOGIC;
               Clear : in STD_LOGIC;
               Binary_state : out STD_LOGIC_vector(1 downto 0);
               Sequence : out STD_LOGIC);
               
               
    end component FSM;
    
    component FSM2 is    
    Port (     clk : in STD_LOGIC;
               Clear : in STD_LOGIC;
               Initial : in STD_LOGIC_VECTOR (7 downto 0) := "00000000"; --initial value of 0
               Final : out STD_LOGIC_VECTOR (7 downto 0);
               Binary_state : out STD_LOGIC_vector(1 downto 0);
               En : in STD_LOGIC);
               
               
    end component FSM2;


signal carry: STD_LOGIC_VECTOR (7 downto 0);  -- Seven Segment Display Signal
signal s_clk: std_logic; -- signal for the slowed clk
signal enabler  : std_logic; -- transfers signal from pressure pads to the bit counter

begin

    SG: sseg_dec PORT MAP(ALU_VAL(0) => carry(0),
                          ALU_VAL(1) => carry(1),
                          ALU_VAL(2) => carry(2),
                          ALU_VAL(3) => carry(3), 
                          ALU_VAL(4) => carry(4),    
                          ALU_VAL(5) => carry(5),       
                          ALU_VAL(6) => carry(6) ,           
                          ALU_VAL(7) => carry(7) ,             
                          CLK => CLK, SEGMENTS => SEG, DISP_EN => AN, SIGN => '0', valid => '1');
    Clock: clk_div2 PORT MAP(clk => clk,sclk => s_clk );
    Steps: FSM PORT MAP(PressureA => PressureA, PressureB => PressureB, clk => clk, Clear => Clear, Binary_state => Led,Sequence => enabler); 
    Bit_counter: FSM2 PORT MAP( clk => clk, Clear => Clear, Binary_state => Led,En => enabler, Initial => carry, Final => carry);

end Behavioral;